Today, I bought a new HDD for my X200.
2.5″ Seagate 500G, it didn’t cost me much, about AUD117.50.
So while I was reinstalling Fedora 11 on my laptop, a colleague of mine asked a question,
“What is the CPU flag that tells the CPU is capable of 64bit?”
Hmm.. the question stumped me, so I started to google and found following site;
http://www.gentoo-wiki.info/Gentoo:/proc/cpuinfo
Also, To outline what those are;
flags
The flags line tells us what extra instructions the processor has to offer. This is a listing of flags with a short explanation of each. There is an even shorter explanation in the file /usr/include/asm/cpufeature.h.
<edit: For F11, the header is in “kernel-devel”, and located in “/usr/src/kernels/$(uname -r)/arch/x86/include/asm/cpufeature.h”>
Intel flags (This table is currently identical with /usr/include/asm/cpufeature.h. Hopefully some hardware god will share his wisdom and expand this table. )
| Flag | Description | Common in processor types |
|---|---|---|
| fpu | Onboard (x87) Floating Point Unit | |
| vme | Virtual Mode Extension | |
| de | Debugging Extensions | |
| pse | Page Size Extensions | |
| tsc | Time Stamp Counter: support for RDTSC and WRTSC instructions | |
| msr | Model-Specific Registers | |
| pae | Physical Address Extensions: ability to access 64GB of memory; only 4GB can be accessed at a time though | |
| mce | Machine Check Architecture | |
| cx8 | CMPXCHG8 instruction | |
| apic | Onboard Advanced Programmable Interrupt Controller | |
| sep | Sysenter/Sysexit Instructions; SYSENTER is used for jumps to kernel memory during system calls, and SYSEXIT is used for jumps back to the user code | |
| mtrr | Memory Type Range Registers | |
| pge | Page Global Enable | |
| mca | Machine Check Architecture | |
| cmov | CMOV instruction | |
| pat | Page Attribute Table | |
| pse36 | 36-bit Page Size Extensions: allows to map 4 MB pages into the first 64GB RAM, used with PSE. | |
| pn | Processor Serial-Number; only available on Pentium 3 | |
| clflush | CLFLUSH instruction | |
| dtes | Debug Trace Store | |
| acpi | ACPI via MSR | |
| mmx | MultiMedia Extension | |
| fxsr | FXSAVE and FXSTOR instructions | |
| sse | Streaming SIMD Extensions. Single instruction multiple data. Lets you do a bunch of the same operation on different pieces of input in a single clock tick. | |
| sse2 | Streaming SIMD Extensions-2. More of the same. | |
| selfsnoop | CPU self snoop | |
| acc | Automatic Clock Control | |
| IA64 | IA-64 processor Itanium. | |
| ht | HyperThreading. Introduces an imaginary second processor that doesn’t do much but lets you run threads in the same process a bit quicker. | |
| nx | No Execute bit. Prevents arbitrary code running via buffer overflows. | |
| pni | Prescott New Instructions aka. SSE3 | |
| vmx | Intel Vanderpool hardware virtualization technology | |
| svm | AMD “Pacifica” hardware virtualization technology | |
| lm | “Long Mode,” which means the chip supports the AMD64 instruction set | |
| tm | “Thermal Monitor” Thermal throttling with IDLE instructions. Usually hardware controlled in response to CPU temperature. | |
| tm2 | “Thermal Monitor 2″ Decrease speed by reducing multipler and vcore. | |
| est | “Enhanced SpeedStep” |
